十进制计数器vhdl

查看文章 VHDL十进制计数器2009-07-14 16:28library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity count10 is port (clk:in std_logic; f:buffer integer range 0 to 15; cout:out std_logic); end; architecture aa of count10 is begin proce